Joint Photographic Experts Group (JPEG) had delivered new image compression algorithm JPEG2000 .Which consider the next generation image compression standard. It is superior to the original JPEG standard in terms of both performance and functionality .This thesis investigates the use of a Field Programmable Gate Array (FPGA) to perform hybrid design for image compression in a JPEG2000 implementation. From JasPer software profiles the wavelets transform DWT and the arithmetic encoding stages of the JPEG2000 algorithm were selected for implementation in hardware. Discrete Wavelet Transform (DWT) design is presented and implemented by using MATLAB in software environment and by using VHDL in hardware environment. The results show that the hardware DWT design is estimated to perform its computation in approximately (3%) of the time needed by the software for the same image data. A schematic design by using Xilinx Foundation (Series 3.1i) program for JPEG2000 arithmetic encoder is presented, suitable for implementation on (XC4028EX2-HQ208) FPGA. The implementation results extracted from this design shows that the arithmetic encoder performs its computation in (40%) of the time needed by the software.Finally, JPEG2000 hardware/software hyprid design investigated in this thesis did not affect to the compression ratio is estimated to perform its computation in approximately (63.75%) of the time needed by the software.